A Parallel Computer Hardware and Software Architecture for Digital Signal Processing

Download or read book A Parallel Computer Hardware and Software Architecture for Digital Signal Processing written by Haluk Gümüşkaya and published by . This book was released on 1995 with total page pages. Available in PDF, EPUB and Kindle. Book excerpt: A parallelization and implementation of digital signal processing (DSP) algorithms using multiprocessors is a special case of parallel processing. This thesis proposes a general hardware and software framework for task partioning, task assignment, processor ( or process) network construction, task scheduling and programming problems of both atomic and large grain data flow graphs describing DSP algorithms for a parallel pipelined architecture which is suitable for many different DSP algorithms. The proposed architecture is a SSIMD or MIMD machine depending on the algorithms implemented and the programming methodoligies.The proposed architecture and its six network configurations are partly implemented as an experimental techniques are proposed for atomic data flow graphs.The simulation and implementation blocks columnization scheduling technique for DSP algorithms described by large grain data flow block diagrams is proposed. It is based on data flow programming techniques using FIFO buffers.The concurency in the proposed scheduling algorithms suitable for this parallel pipelined architecture is both temporal concurency (pipelining), where, chains of tasks are divided into stages, with every stage handling results obtained from the previous stage and spatial concurency (parallelism), where tasks are executed by several PEs simultaneously. The third level of concurency can be also achieved by using input and output synchronized circular buses. This time the system throughput can be at its near theoritical data acquisition throughput limits.The AdEPar hardware and software visual object-oriented DSP environment based on theoretical work presented in this thesis was designed to serve as a test bed for various schduling, similation and code generation problems as well as a real-time implementation tool for DSP systems and advanced studies.